The present invention relates to a tone display voltage generating device for supplying a tone display voltage to a tone display element such as a liquid crystal panel and a plasma display panel, and also relates to a tone display device including such a tone display voltage generating device. Particularly, the invention relates to a tone display voltage generating device which switches modes of charging load capacitors of the tone display element via a selecting circuit such as a DA converter, between a rapid charging mode which utilizes a low output impedance circuit such as a buffer and a power-efficient charging mode which does not utilize the buffer, and also relates to a tone display device including such a tone display voltage generating device.
FIG. 13 is a block diagram showing an arrangement of a liquid crystal display device of the TFT (Thin Film Transistor) system, which is a representative of the active-matrix variety.
The liquid crystal display device includes a liquid crystal display section and a liquid crystal driving unit (liquid crystal driving circuit) for driving the liquid crystal display section. The liquid crystal display section has a liquid crystal panel 901 of the TFT system. The liquid crystal panel 901 includes a plurality of display unit elements (pixels) which are disposed in a matrix pattern, and a counter electrode (common electrode) 906.
The liquid crystal driving unit, on the other hand, includes a source driver 902 and a gate driver 903, each having IC (Integrated Circuit) chips, and a controller 904 and a liquid crystal driving power supply 905.
The source driver 902 and the gate driver 903 are mounted by a common mounting method in which a TCP (Tape Carrier Package) having the IC chips on a film with a predetermined wiring pattern is mounted on ITO (Indium Tin Oxide) terminals which extend from inside toward the periphery of the liquid crystal panel 901. In other cases, the IC chips are directly mounted by heat-bonding on the ITO terminals of the liquid crystal panel 901 via an ACF (Anisotropic Conductive Film).
Further, for miniaturization of the liquid crystal display device, the controller 904, the liquid crystal driving power supply 905, the source driver 902, and the gate driver 903 may be packaged into a single chip, or two to three chips. These members are shown in separate form in FIG. 13 according to their functions.
The controller 904 outputs digital display data (e.g., video signals of R (Red), G (Green), and B (Blue)) indicated by D in FIG. 13 and various control signals indicated by S1 in FIG. 13 to the source driver 902, and outputs various control signals indicated by S2 in FIG. 13 to the gate driver 903. The control signals supplied to the source driver 902 chiefly include a horizontal synchronize signal (latch signal Ls), a start pulse signal, and a clock signal for the source driver. The control signals supplied to the gate driver 903 chiefly include a vertical synchronize signal, and a clock signal for the gate driver. Note that, power supplies for driving the IC chips (gate driver ICs, source driver ICs) are omitted in FIG. 13.
Further, the liquid crystal driving power supply 905 is for supplying a liquid crystal panel display voltage to the source driver 902 and the gate driver 903. As the term is used herein, the liquid crystal panel display voltage refers to a reference voltage for generating a tone display voltage.
Externally inputted display data are inputted to the source driver 902 via the controller 904 in the form of display data D of a digital signal. The source driver 902 samples the inputted display data D in a time sequential manner and stores the sampled data before converting it into a tone display voltage by DA (Digital-Analog) conversion in synchronism with a horizontal synchronize signal (latch signal Ls) which is sent from the controller 904.
The source driver 902 then outputs the resulting tone display analog voltage (tone display voltage) after the DA conversion through the liquid crystal driving voltage output terminals to source signal lines 1004 (see FIG. 14) which are provided in the liquid crystal panel 901.
The following describes a configuration of the liquid crystal panel 901 with reference to FIG. 14. The liquid crystal panel 901 includes pixel electrodes 1001, pixel capacitors 1002, TFTs 1003 as the switching element for switching ON/OFF a voltage applied to the pixels, the source signal lines 1004, gate signal lines 1005, and a counter electrode 1006 (corresponds to the counter electrode 906 of FIG. 13) of the liquid crystal panel. Note that, in FIG. 14, the area indicated by A corresponds to the display unit element of a single pixel.
To the source signal lines 1004 from the source driver 902 of FIG. 13 is applied a tone display voltage of an intensity according to the display brightness of a target pixel. Meanwhile, to the gate signal lines 1005 from the gate driver 903 of FIG. 13 is applied a scanning signal, so that the plurality of TFTs 1003 which are disposed in a vertical direction (i.e., direction of extension of the source signal lines 1004) are switched ON one after another.
While the TFTs 1003 are ON, the tone display voltage is applied from the source signal lines 1004 to the pixel electrodes 1001 which are connected to the drain of the TFTs 1003. This sets off storing charge in the pixel capacitors 1002 between the pixel electrodes 1001 and the counter electrode 1006. The TFTs 1003 are then switched OFF (non-select state) at the end of the selection by the gate signal lines 1005, thus maintaining the applied voltage to the pixel capacitors 1002. The transmission of light at each display unit element (pixel) is thus varied by this ON/OFF operation according to the level of the applied tone display voltage, thus realizing intended tone display.
FIG. 15 and FIG. 16 show exemplary waveforms of liquid crystal driving voltages respectively applied to the source signal lines 1004, the gate signal lines 1005, and the pixel electrodes 1001 of the liquid crystal panel 901 of FIG. 14. In FIG. 15 and FIG. 16, indicated by 1101 and 1201 are waveforms of the tone display voltage which is outputted from the source driver 902 to the source signal lines 1004. Further, indicated by 1102 and 1202 are voltage waveforms of the scanning signal outputted from the gate driver 903 to the gate signal lines 1005 for controlling ON/OFF of the TFTs 1003. Note that, the TFTs 1003 become ON when 1102 or 1202 is at High level, and become OFF when 1102 or 1202 is at Low level.
Further, 1103 and 1203 indicate a potential of the counter electrode 1006 (see FIG. 14), and 1104 and 1204 are waveforms of a voltage applied to the pixel electrodes 1001. The following explains how the voltage waveform 1104 (see FIG. 15 and elsewhere) applied to the pixel electrodes 1001 is varied with respect to a given pixel.
First, the TFT 1003 is switched ON when the scanning signal 1102 is at High level, and the pixel capacitor 1002 starts charging (i.e., application of the tone display voltage 1101). Then, the TFT 1003 is switched OFF as the scanning signal becomes Low level when the voltage of the pixel capacitor 1002 reaches a predetermined voltage level. This voltage level, corresponding to the stored charge in the pixel capacitor 1002, is maintained until the scanning signal returns to High level. Note that, the voltage waveform indicated by 1204 in FIG. 16 is also varied in this manner.
Note that, the voltage applied to a liquid crystal material (not shown) is the potential difference (voltage) between the pixel electrode 1001 and the counter electrode 1006, which is indicated by the areas of oblique lines in FIG. 15 and FIG. 16.
Further, FIG. 15 and FIG. 16 are different in the voltage values of the tone display voltages (1101, 1201) applied to the source signal lines 1004, so that displayed tones are also different. That is, desired tone display is realized by varying the potential difference (indicated by oblique lines in FIG. 15 and FIG. 16) between the pixel electrode 1001 and the counter electrode 1006 in each pixel by way of varying the voltage value of the tone display voltage. Note that, the number of tones which can be displayed is decided by the number of available voltage levels applied to the liquid crystal material. In other words, the number of tones that can be displayed is decided by the number of available voltage levels of the tone display voltage which is outputted as an analog signal.
Incidentally, the present invention relates to a reference voltage generator and an output circuit in a tone display circuit which makes up a significant portion of the total circuit size and the total power consumption. Therefore, the following explanation will be based on the liquid crystal display unit, particularly with reference to the source driver 902.
FIG. 17 is a block diagram showing an arrangement of the source driver 902. The following describes only the fundamental portions of the source driver 902 with reference to FIG. 17 along with other drawings. The digital display data DR, DG, DB (e.g., each with 6 bits) sent from the controller 904 (see FIG. 13) are temporarily latched in an input latch circuit 1301. Note that, the digital display data DR, DG, and DB correspond to data of red, green, and blue, respectively, and are collectively referred to as display data D in FIG. 13.
Further, from the controller 904, the source driver 902 receives the start pulse signal SP, and the clock signal CK for the source driver. The start pulse signal SP is successively transferred through stages of a shift register 1302 in synchronism with the clock signal CK. The start pulse signal SP has two functions: (1) One is to supply output signals from the respective stages of the shift register 1302 to a sampling memory circuit 1303; and (2) the other is to output a start pulse signal SP (cascade output signal S) for the source driver from the last stage of the shift register 1302 to the source driver on the next stage.
Further, the digital display data DR, DG, DB which were latched in the input latch circuit 1301 are temporarily stored in the sampling memory circuit 1303 in a time sequential manner in synchronism with the output signals which were supplied from the respective stages of the shift register 1302 to the sampling memory circuit 1303. The digital display data DR, DG, DB are then outputted to a hold memory circuit 1304 on the next stage.
More specifically, after the digital display data DR, DG, DB of one horizontal synchronize period (see FIG. 18) are stored, the hold memory circuit 1304 receives the output signals from the respective stages of the sampling memory circuit 1303 in accordance with the horizontal synchronize signal (latch signal Ls) supplied from the controller 904 (see FIG. 13), and outputs the output signals to a level shifter 1305 on the next stage. Further, the hold memory circuit 1304, in addition to this output operation, maintains the digital display data DR, DG, DB until the next horizontal synchronize signal is inputted.
The level shifter 1305 is the circuit which converts the levels of the input signals, for example, by raising their voltage levels, so that they can be suitably inputted into a DA converter 1306 on the next stage which operates to process the levels of applied voltages to the liquid crystal panel 901 (see FIG. 13). Further, a reference voltage generator 1309 generates various analog voltages for tone display in accordance with a reference voltage VR from the liquid crystal driving power supply 905 (see FIG. 13), and outputs the voltages so generated to the DA converter 1306.
The DA converter 1306 selects one of the analog voltages supplied from the reference voltage generator 1309, according to the digital display data which were converted into different levels by the level shifter 1305. The analog voltage which is indicative of a tone is outputted from a liquid crystal driving voltage output terminal (simply xe2x80x9coutput terminalxe2x80x9d hereinafter) 1308, via an output circuit 1307, to the source signal lines 1004 of the liquid crystal panel 901. The output circuit 1307 serves as a buffer, and is made up of a voltage follower circuit using, for example, a differential amplifier.
FIG. 18, FIG. 19(a) and FIG. 19(b) are timing charts of the input signals or output signals of the source driver 902 or the gate driver 903 (see FIG. 13) which were described with reference to FIG. 13 through FIG. 17. As shown in FIG. 18, the vertical synchronize signal inputted to the gate driver 903 from the controller 904 and the horizontal synchronize signal (latch signal Ls) inputted to the source driver 902 are outputted in a predetermined relationship. Further, the scanning signals outputted from the gate driver 903 to the gate signal lines G1 through Gn (correspond to the gate signal lines 1005 of FIG. 14) respectively have select pulses (voltage signal of High level shown in FIG. 16), one in each vertical synchronize period, which occur one after another in synchronism with the horizontal synchronize signal.
Further, there is a relationship, as described above, in the signal waveforms of the scanning signal, the clock signal CK for tone display, the start pulse SP, the digital display data DR, DG, DB (labelled xe2x80x9cdigital display data signalxe2x80x9d in FIG. 19(a)), and the horizontal synchronize signal, as shown in FIG. 19(a). Further, there is a relationship in signal waveforms (labelled xe2x80x9csource driver outputxe2x80x9d in FIG. 19(b)) outputted to the source signal lines 1004 from the output terminals 1308 of the source driver 902, as shown in FIG. 19(b). Note that, shown in FIG. 19(b) is an example in which the output terminals 1308 of the source driver 902 include a total of 300 terminals X1 through X100, Y1 through Y100, and Z1 through Z100 (i.e., 100 terminals for each color of R, G, B). This enables tone display of 64 patterns as will be explained later.
The following describes circuit structures of the reference voltage generator 1309, the DA converter 1306, and the output circuit 1307 in more detail, which are particularly relevant to the present invention, with reference to FIG. 17, FIG. 20, FIG. 21, and FIG. 22.
FIG. 20 is an exemplary circuit structure of the reference voltage generator 1309. In the case where the digital display data DR, DG, DB of the respective colors of RGB are, for example, data of 6 bits, respectively, then the reference voltage generator 1309 outputs 64 analog voltages, corresponding to tones of 26=64 patterns. The following describes a specific structure of this case.
The reference voltage generator 1309 adopts a structure of the simplest form, in which a resistance divider including serially connected resistances R0 through R7 makes up the reference voltage generator 1309. Further, each of the resistances R0 through R7 is made up of serially connected eight resistance elements. For example, taking resistance R0 as an example, as shown in FIG. 21, the resistance R0 is made up of serially connected eight resistance elements R01, R02, . . . , R08. This structure remains the same for the other resistances R1 through R7 as well. Therefore, the structure of the reference voltage generator 1309 can be regarded as the serial connection of a total of 64 resistance elements. The resistance values of resistances R0 through R7 are set by taking into account the effect of xcex3 correction, etc., as will be explained later.
Further, the reference voltage generator 1309 includes nine half-tone voltage input terminals which correspond to nine reference voltages Vxe2x80x20, Vxe2x80x28, . . . , Vxe2x80x256, Vxe2x80x264. The half-tone voltage input terminal corresponding to the reference voltage Vxe2x80x264 is connected to one end of the resistance R0. The other end of the resistance R0, i.e., the junction of resistance R0 and resistance R1, is connected to the half-tone voltage input terminal corresponding to the reference voltage Vxe2x80x256. In the same manner, the half-tone voltage input terminals corresponding to the reference voltages Vxe2x80x248, Vxe2x80x240, . . . , Vxe2x80x28 are respectively connected to the junctions of resistances R1 and R2, R2 and R3, . . . , R6 and R7 adjacent to each other. Further, the half-tone voltage input terminal corresponding to the reference voltage Vxe2x80x20 is connected to the opposite end of the junction of the resistances R6 and R7.
This structure enables voltages V1 through V63 to be obtained from adjacent pairs of the 64 resistance elements. In addition, these voltages V1 through V63, combined with voltage V0 which is directly obtained from the reference voltage Vxe2x80x20, gives tone display analog voltages (voltages V0 through V63) of 64 patterns. That is to say, in the reference voltage generator 1309 which is made up of resistance dividers, the tone display analog voltages V0 through V63 are decided by the resistance ratio. The analog voltages of 64 levels (voltages V0 through V63) are inputted to the DA converter 1306 from the reference voltage generator 1309.
It should be noted here that, generally, the reference voltages Vxe2x80x20 and Vxe2x80x264 at the both ends of the voltage range are always inputted to the half-tone voltage input terminals. However, seven half-tone voltage input terminals corresponding to the remaining reference voltages Vxe2x80x28 through Vxe2x80x256 are used for the purpose of fine adjustment, and it is not necessarily the case that voltages are inputted to these terminals.
The following describes the DA converter 1306. FIG. 22 shows an exemplary structure of the DA converter 1306. A structure of the output circuit 1307 is also shown in FIG. 22.
The DA converter 1306 includes MOS transistors or transmission gates as analog switches (xe2x80x9cswitchesxe2x80x9d hereinafter), and selects and outputs one of the inputted 64 voltages V0 through V63 according to display data of a 6-bit digital signal. That is, the switches are switched ON or OFF according to the bits (Bit 0 to Bit 5) of the display data of a 6-bit digital signal. That is, one of the inputted 64 voltages is selected and outputted to the output circuit 1307. The following explains how this is carried out.
The 6-bit digital signal is such that Bit 0 is the LSB (Least Significant Bit) and Bit 5 is the MSB (Most Significant Bit). The switches are provided in pairs. Bit 0 corresponds to 32 pairs of switches (64 switches), and Bit 1 corresponds to 16 pairs of switches (32 switches). Subsequently, the number of switches becomes half for each subsequent bit, and thus Bit 5 corresponds to a single pair of switches (2 switches). Therefore, there exists a total of 25+24+23+22+21+1=63 pairs of switches (126 switches).
One end of the switches which correspond to Bit 0 make up terminals for receiving the voltages V0 through V63. The other end of these switches are connected to each other in pairs and connected to one end of the switches which correspond to Bit 1. This structure is repeated for each group of switches up to the pair of switches corresponding to Bit 5. The switches corresponding to Bit 5 eventually lead to a single transmission line which is connected to the output circuit 1307.
The groups of switches corresponding to Bit 0 to Bit 5 will be called switch groups SW0 through SW5, respectively. Each switch of the switch groups SW0 through SW5 is controlled by the 6-bit digital display data (Bit 0 to Bit 5) in the following manner.
In the switch groups SW0 through SW5, one of each pair of analog switches (lower switch in FIG. 22) becomes ON when the corresponding Bit is 0 (Low level). Conversely, the other switch (upper switch in FIG. 22) becomes ON when the corresponding Bit is 1 (High level). In FIG. 22, Bit 0 to Bit 5 are (111111), and the upper switch is ON and the lower switch is OFF in all pairs of switches. In this case, the DA converter 1306 outputs voltage V63 to the output circuit 1307.
In the same manner, for example, the DA converter 1306 outputs voltage V62 to the output circuit 1307 when Bit 5 to Bit 0 are (111110), and outputs V1 when (000001), and V0 when (000000). In this manner, one of the tone display analog voltages (voltages V0 to V63) for digital display is selectively outputted so as to realize tone display.
The reference voltage generator 1309 is usually provided for each source driver IC and is shared. On the other hand, the DA converter 1306 and the output circuit 1307 are provided for each output terminal 1308 (FIG. 17).
Further, in the case of color display, since the output terminal 1308 corresponds to each color in this case, the DA converter 1306 and the output circuit 1307 are provided for each pixel and for each color. That is, when the number of pixels in a direction of a longer side of the liquid crystal panel 90 is N, the output terminals 1308 of red, green, and blue are denoted with subscript n (n=1, 2, . . . , N) by R1, G1, B1, R2, G2, B2, . . . , RN, GN, BN. Thus, there will be required 3N DA converters 1306 and 3N output circuits 1307.
Further, in order to realize intended tone display, xcex3 correction is commonly employed. For example, xcex3 correction is carried out by varying the resistance values of the serially connected eight resistances R0, R1, . . . , R6, R7 making up the reference voltage generator 1309, so that the respective values of the outputted analog voltages (tone display reference voltages) become non-linear, which gives non-linear characteristics to the transmission characteristics of the liquid crystal panel (liquid crystal display element).
FIG. 26(a) shows an example of a relationship between the digital display data and the analog voltages (tone display reference voltages) after xcex3 correction, where the vertical axis indicates, in order of magnitude, the 64 analog voltages (voltages V0 to V63) generated by the reference voltage generator 1309, and the horizontal axis indicates the 6-bit digital display data used to perform display of 64 tones. Note that, for clarity, the digital display data is indicated by hexadecimal numerals in FIG. 26(a), which nonetheless correspond to binary numerals in an ordinary manner such that 000000 (00h), . . . , 001000 (08h), . . . , 111000 (38h), . . . , 111111 (3Fh).
For example, when the digital display data is 00h, as described earlier, voltage V0 is selectively outputted from the DA converter 1306, and when the digital display data is 08h, voltage V8 is selectively outputted from the DA converter 1306. These voltages are outputted to the liquid crystal panel 901 via the output circuit 1307.
Further, as explained above, each of the resistances R0, R1, . . . , R6, R7 is made up of the serially connected eight resistance elements of the same resistance value, and therefore the xcex3 correction characteristics of the liquid crystal panel 901 show the kinked characteristics as shown in FIG. 26(a).
Meanwhile, in liquid crystal display devices, it is known that reliability of the liquid crystal material or other members suffers when a voltage of the same polarity is applied to the liquid crystal panel (liquid crystal display element) as the liquid crystal driving voltage for extended periods of time. This is avoided by adopting AC driving so that the polarity of the liquid crystal driving voltage applied to each pixel of the liquid crystal display element is reversed at certain time intervals, so as to average the voltages applied to the respective pixels of the liquid crystal display element.
In reversing the applied voltages (including the liquid crystal driving voltage) to the liquid crystal, the digital display data also need to be reversed accordingly. The following describes how this is achieved, for example, based on a method of reversing the digital display data in positive polarity driving (when the liquid crystal driving voltage has a positive polarity), and a method of reversing the digital display data in negative polarity driving (when the liquid crystal driving voltage has a negative polarity).
In these methods, the digital display data of binary numerals is reversed from xe2x80x9c1xe2x80x9d to xe2x80x9c0xe2x80x9d, or from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d. For example, digital display data 000000 (00h) used in positive polarity driving is converted to digital display data 111111 (3Fh) for negative polarity driving, or digital display data 001000 (08h) used in positive polarity driving is converted to digital display data 110111 (37h) used for negative polarity driving. That is, when the digital display data 00h, 08h, . . . , 38h, 3Fh as shown in FIG. 26(a) are regarded as the digital display data for positive polarity driving, and when these digital display data are reversed to the digital display data for negative polarity driving, then these data become the digital display data 3Fh, 37h, . . . , 07h, 00h as shown in FIG. 26(b). Note that, FIG. 26(b) shows an example of a relationship between the digital display data and the analog voltages after xcex3 correction, when the digital display data for positive polarity driving as shown in FIG. 26(a) are reversed to the digital display data for negative polarity driving.
This reversion of digital display data can easily be realized, for example, by selecting whether the output of a flip/flop circuit F/F (not shown) which makes up the hold memory circuit 1304 in the source driver 902 is from a forward output terminal Q or from a reverse output terminal/Q. The voltage applied to the counter electrode of the liquid crystal panel 901 is, for example, a ground voltage (0 V) in positive polarity driving, and is the predetermined voltage V64 in negative polarity driving.
Thus, for example, in positive polarity driving with the digital display data 00h, the DA converter 1306 selects the voltage V0 corresponding to this data 00h. As a result, a voltage (V0-0 (V)) is applied to the selected pixel of the liquid crystal panel 901. On the other hand, in negative polarity driving, the DA converter 1306 selects the voltage V63 corresponding to the digital display data 3Fh which was obtained by reversing the digital display data 00h. As a result, a voltage (.V63 -V64) is applied to the selected pixel of the liquid crystal panel 901.
Note that, in this example, the voltage levels are assumed to be V64 greater than V63 greater than , . . . ,  greater than V0 greater than 0 (V), and therefore the AC driving is such that the polarity of the liquid crystal driving voltage applied to the selected pixel is periodically changed between positive polarity driving and negative polarity driving. Apparently, not only the digital display data 00h but also the other digital display data are subject to this AC driving.
Incidentally, the digital display data are reversed in the foregoing AC driving. However, as described below, the AC driving may also be carried out without reversing the digital display data. For example, in the reference voltage generator 1309 as shown in FIG. 20, in positive polarity driving, the reference voltage Vxe2x80x20 and the reference voltage Vxe2x80x264 are inputted to their corresponding input terminals, respectively, and the potential of the counter electrode 906 of the liquid crystal panel 901 is set to ground potential, for example.
On the other hand, when reversing the polarity, i.e., in negative polarity driving, in the reference voltage generator 1309, the reference voltage Vxe2x80x264 and the reference voltage Vxe2x80x20 are inputted to the input terminal of the reference voltage Vxe2x80x20 and the input terminal of the reference voltage Vxe2x80x264, respectively, and the predetermined voltage V64 is applied to the counter electrode 906 of the liquid crystal panel 901, thereby carrying out the AC driving for periodically changing the polarity of the liquid crystal driving voltage applied to the selected pixel.
Note that, as described earlier, in the reference voltage generator 1309 as shown in FIG. 20, the half-tone voltage input terminals of the reference voltages Vxe2x80x28, Vxe2x80x216, . . . Vxe2x80x248, Vxe2x80x256 are used for fine adjustment of output voltages, and thus, under normal conditions, these input terminals remain unconnected, i.e., an opened state. In the foregoing AC driving of the liquid crystal panel 901, the described methods are all an example of polarity reversion of liquid crystal driving in which the xcex3 correction characteristics remain the same irrespective of the polarity of the liquid crystal driving.
However, depending on characteristics of the liquid crystal display element (liquid crystal panel), there are cases where the required xcex3 correction characteristics may become different when the polarity of the liquid crystal driving is changed. In this case, such different xcex3 correction characteristics are accommodated by inputting predetermined voltages also to the half-tone voltage input terminals of the reference voltages Vxe2x80x28, Vxe2x80x216, . . . , Vxe2x80x248, Vxe2x80x256 of the reference voltage generator 1309 only in either one of positive polarity driving and negative polarity driving. As an specific example, in the system where the digital display data are reversed between positive polarity driving and negative polarity driving, the xcex3 correction characteristics of FIG. 26(a) and the xcex3 correction characteristics of FIG. 26(b) are used in the positive polarity driving and the negative polarity driving, respectively. Note that, here, the xcex3 correction characteristics are changed at the time of polarity reversion by changing the analog voltage values outputted from the reference voltage generator 1309, by way of applying predetermined voltages to the two half-tone voltage input terminals of reference voltages Vxe2x80x28 and Vxe2x80x256 (see FIG. 26(c)).
The following describes various ways to connect the reference voltage generator 1309, the DA converter 1306, and the output circuit 1307, which is provided as required, with reference to FIG. 23 through FIG. 25.
The example of connection as shown in FIG. 23 is an overview of the arrangements of FIG. 20 and FIG. 21, wherein the DA converter 1306 which receives the tone display voltages V0 through V63 from the reference voltage generator 1309 selects a tone display voltage according to the inputted digital display data (output signal from the level shifter), and outputs the selected voltage to the output circuit 1307.
This output is then supplied to the source signal lines 1004 in the liquid crystal panel via the output circuit 1307, which serves as a buffer, through the output terminals 1308. Note that, in FIG. 23, indicated by 1008 is a model showing a pixel of the liquid crystal panel and a wire capacitor of a source signal line 1004 connected thereto. Here, 1002 indicates the pixel capacitor, 1003 the TFT, 1006 the potential of the counter electrode, and 1007 the wire capacitor of the source signal line 1004.
As described, the circuit structure of FIG. 23 is adapted (1) to obtain voltages V0 through V63 of different levels from the resistance dividers which are made up of a plurality of serially connected resistances, (2) to select a voltage from the voltages V0 through V63 by the analog switches according to the digital display data, and (3) to output the voltage thus selected at low impedance via the output circuit 1307 which serves as a buffer, so as to charge the wire capacitor 1007 of the source signal line 1004, or the pixel capacitor 1002 in the liquid crystal panel.
Further, as shown in FIG. 24, the output circuit 1307 may be omitted from the circuit structure of FIG. 23. In this case, the circuit is adapted (1) to obtain voltages V0 through V63 of different levels from the resistance dividers which are made up of a plurality of serially connected resistances, (2) to select a voltage from the voltages V0 through V63 by the analog switches according to the digital display data, and (3) to directly input the voltage thus selected to the source signal line 1004, so as to charge the wire capacitor 1007 or the pixel capacitor 1002.
Further, as shown in FIG. 25, it is possible to have a circuit structure in which buffers 1310, equivalent to the output circuit 1307, electrically connects the reference voltage generator 1309 and the DA converter 1306, so that the buffers 1310 are provided for the respective voltage lines carrying the voltages V0 to V63. In this case, the voltages V0 to V63 are inputted to the DA converter 1306 at low impedance via their respective buffers 1310, and a voltage which corresponds to the digital display data is selected by the analog switches, so as to charge the wire capacitor 1007 or the pixel capacitor 1002.
Incidentally, as described earlier, the reference voltage generator 1309 is usually provided for each source driver IC, and is shared, whereas the DA converter 1306 and the output circuit 1307 are provided for each output terminal 1308 (see FIG. 23 to FIG. 25).
For example, each source driver IC (source driver 902) as shown in FIG. 17 has 300 output terminals 1308 (X1 to X100, Y1 to Y100, Z1 to Z100). Given this, the number of output terminals 1308 per source driver IC is expected to increase with the advancement of smaller and thinner liquid crystal display devices and finer pitched liquid crystal panels.
For example, in the circuit structure as shown in FIG. 23, the output circuit 1307 is provided for each output terminal 1308. This increases the layout area and thus the chip area of the source driver IC chip, resulting in higher cost. Further, the buffer (FIG. 25) or the output circuit 1307 (FIG. 23) which serves as the buffer comprises an analog circuit such as the differential amplifier. This requires an operation current for example, and the power consumption is generally increased. That is, in the circuit structure in which the output circuit 1307 of multiple stages is provided, the power consumed by the output circuit 1307 becomes an obstacle for reducing power consumption of the source driver IC.
The circuit structure as shown in FIG. 24 is adapted to reduce power consumption by omitting the output circuit 1307. Here, in order to charge the wire capacitor 1007 of the source signal line 1004 or the pixel capacitor 1002 within a predetermined time period (one scanning period), the respective resistance values of the resistance dividers provided in the reference voltage generator 1309 need to be reduced. The source signal lines 1004 in particular stretch over the liquid crystal panel from the upper portion to the lower portion of the panel as shown in FIG. 14, and therefore the capacitance of the wire capacitor 1007 is relatively large already. However, the smaller resistance values of the resistance dividers always require a large current through the resistance dividers. Such a current flow adds up to a reactive current to increase power consumption.
Further, reversion of the polarity of the liquid crystal driving voltage applied to the liquid crystal panel (liquid crystal display element) 901 may result in a change in xcex3 correction characteristics, depending on characteristics of the liquid crystal display element. One way of solving this problem is to apply predetermined voltages through the other half-tone voltage input terminals (unused terminals before the polarity reversion) of the reference voltage generator 1309. However, this requires additional pads (electrodes), corresponding to the number of the half-tone voltage input terminals, on the IC chip (here, source driver IC) and thus, providing these pads increases a chip area of the IC chip.
Further, in the case of using the half-tone voltage input terminals of the reference voltages Vxe2x80x28, Vxe2x80x216, . . . , Vxe2x80x248, Vxe2x80x256 (also referred to as half-tone voltages), the liquid crystal driving power supply 905 of the liquid crystal display device as shown in FIG. 13 additionally requires a half-tone voltage supply circuit for supplying these reference voltages Vxe2x80x28, Vxe2x80x216, . . . Vxe2x80x248, Vxe2x80x256. Further, since the reference voltages Vxe2x80x28, Vxe2x80x216, . . . , Vxe2x80x248, Vxe2x80x256 need to be supplied at low impedance, larger transistors, etc., are required at the output section. These factors further increase the size of liquid crystal driving power supply 905.
Further, the use of the half-tone voltages requires a large number of half-tone voltage wires for electrically connecting the liquid crystal driving power supply 905 with the respective source driver ICs. This increases the wiring area, resulting in further increase in size of the liquid crystal display device.
Further, such a large number of half-tone voltage wires makes it difficult to properly provide the wires. As a result, external noise enters these half-tone voltage wires, for example, from the clock of the source driver, which may result in poor display quality of the liquid crystal display device.
Further, the circuit structure as shown in FIG. 25 is adapted to further reduce power consumption than that by the structure of FIG. 23 by providing the buffers 1310, which are equivalent to the output circuit 1307, for the respective output stages of the tone display voltages of the reference voltage generator 1309 which is commonly provided for each source driver IC. Further, compared with the structure of FIG. 24, the resistance values of the resistance dividers in the reference voltage generator 1309 can be further increased, thus reducing the reactive current.
However, if the circuit structure of FIG. 25 were to adapt to display of 64 tones for example (FIG. 18), it will be required to provide a total of 64 buffers 1310 for the respective output stages of the tone display voltages (voltages V0 through V63) of the reference voltage generator 1309, or the buffer 1310 needs to be provided for each output of 8-tone display, i.e., for each of eight lines between eight half-tone voltage input terminals of the reference voltages Vxe2x80x20 to Vxe2x80x256 and resistance dividing means. That is, the circuit structure of FIG. 25 still requires a plurality of buffers 1310 proportional to the number of display tones or the number of tones.
Incidentally, it has become common in recent years to actively employ the TFT system even for battery-powered liquid crystal display devices of a small size which are often incorporated in portable terminals. In this connection, driving devices which consume less power are in demand to encourage development of these applications. Therefore, there is strong need to reduce the number of output circuits 1307 or buffers 1310 which consume relatively large power, and to develop a driving circuit which is capable of stably performing tone display without constant supply of a large current to the reference voltage generator 1309.
The present invention was made in view of the foregoing problems, and an object of the present invention is to provide a tone display voltage generating device which switches modes of charging load capacitors of a tone display element, for example, from a tone power supply (reference voltage generating means), which is made up of resistance dividers, via selecting means such as a DA converter, between a rapid charging mode which utilizes a low output impedance circuit such as a buffer (buffer means) and a power-efficient charging mode which does not utilize the buffer, and also to provide a tone display device including such a tone display voltage generating device.
Another object of the present invention is to provide a tone display voltage generating device which accurately outputs a predetermined voltage without consuming large power by successively and time-sequentially switching tone display voltages of different levels which are outputted to the selecting means via the low output impedance circuit, and also to provide a tone display device including such a tone display voltage generating device.
In order to achieve the foregoing objects, a tone display voltage generating device according to the present invention, in an arrangement including reference voltage generating means for generating tone display voltages of different levels according to the number of bits of display data, and selecting means for selecting a voltage from the tone display voltages of different levels according to the display data so as to output the selected voltage to a tone display element, comprises: at least one buffer means with a lower output impedance with respect to the reference voltage generating means; switching means for switching a state of connection between an output stage (voltage drawing section) of the reference voltage generating means, the buffer means, and an input stage of the selecting means, so as to select whether to utilize the buffer means or not when outputting the tone display voltages from the reference voltage generating means to the selecting means; and first control means for controlling switching operations of the switching means according to a state of tone display of the tone display element, the at least one buffer means, the switching means, and the first control means being provided between the output stage of the reference voltage generating means and the input stage of the selecting means.
According to this arrangement, the tone display voltage can be outputted from the reference voltage generating means to the selecting means by utilizing or without utilizing the buffer means of a low output impedance. For example, by outputting the tone display voltage via the buffer means of a low output impedance, load capacitors (e.g., pixel capacitors) of the tone display element such as the liquid crystal panel or plasma display panel can be rapidly charged, thereby reducing charging time.
On the other hand, when the load capacitors have been charged and are in a steady state, the tone display voltage is outputted from the reference voltage generating means to the selecting means without utilizing the buffer means which consumes relatively large power. As a result, power consumption of the tone display voltage generating means can be reduced.
That is, it is possible to provide a tone display voltage generating device which can select a mode of supplying the tone display voltage to the selecting means, either from a rapid supply mode or a power-efficient supply mode.
Further, in order to achieve the foregoing objects, a tone display device according to the present invention includes a tone display voltage generating device of the foregoing arrangement, and a tone display element which carries out tone display by the tone display voltages which are supplied from the tone display voltage generating device.
According to this arrangement, it is possible to provide a tone display device which can carry out tone display according to display data both rapidly and at low power consumption on a tone display element such as a liquid crystal panel or plasma display device.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.